diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index ffc8c3c19a32b4..e879df2f2d9ce6 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -4693,10 +4693,10 @@ void SelectionDAGBuilder::visitFence(const FenceInst &I) { const TargetLowering &TLI = DAG.getTargetLoweringInfo(); SDValue Ops[3]; Ops[0] = getRoot(); - Ops[1] = DAG.getConstant((unsigned)I.getOrdering(), dl, - TLI.getFenceOperandTy(DAG.getDataLayout())); - Ops[2] = DAG.getConstant(I.getSyncScopeID(), dl, - TLI.getFenceOperandTy(DAG.getDataLayout())); + Ops[1] = DAG.getTargetConstant((unsigned)I.getOrdering(), dl, + TLI.getFenceOperandTy(DAG.getDataLayout())); + Ops[2] = DAG.getTargetConstant(I.getSyncScopeID(), dl, + TLI.getFenceOperandTy(DAG.getDataLayout())); DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops)); } diff --git a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td index 459b53923625d6..27e1d8ee6b985c 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td +++ b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td @@ -15,9 +15,9 @@ //===---------------------------------- let AddedComplexity = 15, Size = 0 in def CompilerBarrier : Pseudo<(outs), (ins i32imm:$ordering), - [(atomic_fence imm:$ordering, 0)]>, Sched<[]>; -def : Pat<(atomic_fence (i64 4), (imm)), (DMB (i32 0x9))>; -def : Pat<(atomic_fence (imm), (imm)), (DMB (i32 0xb))>; + [(atomic_fence timm:$ordering, 0)]>, Sched<[]>; +def : Pat<(atomic_fence (i64 4), (timm)), (DMB (i32 0x9))>; +def : Pat<(atomic_fence (timm), (timm)), (DMB (i32 0xb))>; //===---------------------------------- // Atomic loads diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index 79bbbc1eab605d..32c05ae10b6baa 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -86,7 +86,7 @@ defm V_INTERP_MOV_F32 : VINTRP_m < //===----------------------------------------------------------------------===// def ATOMIC_FENCE : SPseudoInstSI< (outs), (ins i32imm:$ordering, i32imm:$scope), - [(atomic_fence (i32 imm:$ordering), (i32 imm:$scope))], + [(atomic_fence (i32 timm:$ordering), (i32 timm:$scope))], "ATOMIC_FENCE $ordering, $scope"> { let hasSideEffects = 1; let maybeAtomic = 1; diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index 1cab1747ff4e25..3efe85a7d45ca0 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -6242,7 +6242,7 @@ def CMP_SWAP_64 : PseudoInst<(outs GPRPair:$Rd, GPR:$temp), } def CompilerBarrier : PseudoInst<(outs), (ins i32imm:$ordering), NoItinerary, - [(atomic_fence imm:$ordering, 0)]> { + [(atomic_fence timm:$ordering, 0)]> { let hasSideEffects = 1; let Size = 0; let AsmString = "@ COMPILER BARRIER"; diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.td b/llvm/lib/Target/AVR/AVRInstrInfo.td index 3de28ead41769e..acf991dcfbb1fa 100644 --- a/llvm/lib/Target/AVR/AVRInstrInfo.td +++ b/llvm/lib/Target/AVR/AVRInstrInfo.td @@ -1310,7 +1310,7 @@ def AtomicLoadOr16 : AtomicLoadOp16; def AtomicLoadXor8 : AtomicLoadOp8; def AtomicLoadXor16 : AtomicLoadOp16; def AtomicFence : Pseudo<(outs), (ins), "atomic_fence", - [(atomic_fence imm, imm)]>; + [(atomic_fence timm, timm)]>; // Indirect store from register to data space. def STSKRr : F32DM<0b1, diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td index 8f41bbfcda72dd..b02e676bc23fe1 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -3293,10 +3293,10 @@ def : Pat<(f64 (fpextend f32:$src)), // source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html // The rule for seq_cst is duplicated to work with both 64 bits and 32 bits // versions of Power. -def : Pat<(atomic_fence (i64 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>; -def : Pat<(atomic_fence (i32 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>; -def : Pat<(atomic_fence (imm), (imm)), (SYNC 1)>, Requires<[HasSYNC]>; -def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>; +def : Pat<(atomic_fence (i64 7), (timm)), (SYNC 0)>, Requires<[HasSYNC]>; +def : Pat<(atomic_fence (i32 7), (timm)), (SYNC 0)>, Requires<[HasSYNC]>; +def : Pat<(atomic_fence (timm), (timm)), (SYNC 1)>, Requires<[HasSYNC]>; +def : Pat<(atomic_fence (timm), (timm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>; let Predicates = [HasFPU] in { // Additional FNMSUB patterns: -a*c + b == -(a*c - b) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 1d7f870721817b..1d20dbf4a60356 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -1019,13 +1019,13 @@ defm : StPat, Requires<[IsRV32]>; // Manual: Volume I. // fence acquire -> fence r, rw -def : Pat<(atomic_fence (XLenVT 4), (imm)), (FENCE 0b10, 0b11)>; +def : Pat<(atomic_fence (XLenVT 4), (timm)), (FENCE 0b10, 0b11)>; // fence release -> fence rw, w -def : Pat<(atomic_fence (XLenVT 5), (imm)), (FENCE 0b11, 0b1)>; +def : Pat<(atomic_fence (XLenVT 5), (timm)), (FENCE 0b11, 0b1)>; // fence acq_rel -> fence.tso -def : Pat<(atomic_fence (XLenVT 6), (imm)), (FENCE_TSO)>; +def : Pat<(atomic_fence (XLenVT 6), (timm)), (FENCE_TSO)>; // fence seq_cst -> fence rw, rw -def : Pat<(atomic_fence (XLenVT 7), (imm)), (FENCE 0b11, 0b11)>; +def : Pat<(atomic_fence (XLenVT 7), (timm)), (FENCE 0b11, 0b11)>; // Lowering for atomic load and store is defined in RISCVInstrInfoA.td. // Although these are lowered to fence+load/store instructions defined in the diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td index 7ebfef4ced8ddc..f26f4a1c1a84c1 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.td +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td @@ -1676,10 +1676,10 @@ def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>; // store bar for all atomic_fence in V8. let Predicates = [HasNoV9] in - def : Pat<(atomic_fence imm, imm), (STBAR)>; + def : Pat<(atomic_fence timm, timm), (STBAR)>; let Predicates = [HasV9] in - def : Pat<(atomic_fence imm, imm), (MEMBARi 0xf)>; + def : Pat<(atomic_fence timm, timm), (MEMBARi 0xf)>; // atomic_load addr -> load addr def : Pat<(i32 (atomic_load_8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;